1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming PFET devices with different structures and performance characteristics.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. A basic field effect transistor comprises a source region, a gate region and a channel region positioned between the source and drain regions. Such a transistor further includes a gate insulation layer positioned above the channel region and a gate electrode positioned above the gate insulation layer. When an appropriate voltage is applied to the gate electrode, the channel region becomes conductive and current may flow from the source region to the drain region. In many cases, the gate electrodes are made of polysilicon. The basic structure of a field effect transistor is typically formed by forming various layers of material and thereafter patterning those layers of material using known photolithography and etching processes. Various doped regions, e.g., source regions, drain regions, halo regions, etc., are typically formed by performing one or more ion implantation processes through a patterned mask layer using an appropriate dopant material, e.g., an N-type dopant or a P-type dopant, to implant the desired dopant material into the substrate. The particular dopant selected depends on the specific implant region being formed and the type of device under construction, i.e., an NFET transistor or a PFET transistor. During the fabrication of complex integrated circuits millions of transistors, e.g., NFET transistors and/or PFET transistors are formed on a substrate by performing a number of process operations.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NFET transistors and create a compressive stress in the channel region for PFET transistors). One performance-enhancing technique that has been employed in manufacturing PFET transistors involves the use of a silicon germanium channel layer. Such a silicon germanium channel layer is typically formed by forming a recess in an active region of a substrate where such a PFET transistor will be formed and thereafter, performing an epitaxial deposition process to form a layer of silicon germanium in the recess. Other semiconductor devices, such as NFET transistors that are being formed on the same substrate, are typically masked while the silicon germanium channel layer is being formed for the PFET transistors. The incorporation of the silicon germanium channel layer enhances the performance of the PFET transistor by bringing the threshold voltage of the device to a desired level (adjusting the work function to the needs of high-K metal gates).
As noted earlier, a typical integrated circuit product may include millions of PFET transistors. However, not all of the PFET transistors perform the same function. That is, in some cases, it would be desirable for the PFET transistors on a substrate to have different performance characteristics. For example, by adjusting the threshold voltage of the PFET transistors with implantations and different mask layers, one can either form a high threshold voltage (low off-current, low performance due to the reduced on-current) device or a low threshold voltage device (high on-current, high performance, but also higher off-current). For high-K metal gate PFETs this approach has the drawback that very high implant doses and counter-doping are required and still the threshold voltage shift attributed to the dose and thickness chosen for the silicon germanium region would present the major and limiting factor for the achievable threshold voltage range and the transistor performance.
To avoid the drawbacks of high implant doses like e.g. high cost, long processing times and high implant damage of the substrate and to allow a wider range of achievable threshold voltages for the high-K metal gate PFETs, the formation of individual silicon germanium regions tailored for the individual performance requirements of the PFETs is needed.
The present disclosure is directed to various methods of forming PFET devices with different structures and performance characteristics that may at least reduce or eliminate one or more of the problems identified above.